Name
Abstract | ||
|---|---|---|
In this paper, we propose a greedy algorithm to minimize the maximal propagation delay for giving the topology of a multi-source multi-sink bus with RLC delay model. The algorithm minimizes the maximal delay by inserting signal repeaters into the critical path and adjusts their sizes, and repeats the above procedure until no any improvement in delay reduction. Experimental results exhibit that the algorithm can reduce the critical delay of a bus effectively for deep submicron technologies. The average savings in critical delay of RLC-based buses for 0.35 mu m and 0.18 mu m technologies are less 5.6% and 4% than that of RC-based buses, respectively, whereas the usages in size of RLC-based buses for 0.35 mu m and 0.18 mu m technologies are less 3.2 and 13.2 than that of RC-based buses, respectively. The average errors compared with HSPICE in critical delay of RLC-based buses for 0.35 mu m and 0.18 mu m technologies are better 3.53% and 1.09% than that of RC-based buses, respectively. The algorithm is simple but very effective. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/APCCAS.2006.342398 | 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS |
Keywords | DocType | Citations |
repeater insertion, bus, RLC delay model | Conference | 4 |
PageRank | References | Authors |
0.57 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-chun Tsai | 1 | 109 | 23.04 |
| Jan-ou Wu | 2 | 12 | 4.53 |
| Trong-yen Lee | 3 | 98 | 20.70 |
| Rong-shue Hsiao | 4 | 21 | 3.34 |