Paper Info
Title
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs
Abstract
This paper1 proposes a novel methodology for improving the leakage yield of digital circuits in the presence of process variations and under probabilistic timing constraints. The leakage minimization problem is formulated as a discrete optimization problem, where a suitable configuration for each gate in the circuit is selected from a standard-cell library consisting of different implementations of each type of gate. A function of mean and variance of the circuit leakage is minimized with constraint on á-percentile of the delay using physical delay models. Since the leakage is a strong function of the threshold voltage and gate length, considering them as design variables in addition to gate sizes can provide significant power savings. We propose efficient techniques for computing delay and leakage power gradients which form the basis of the optimization algorithm. Results on various trade-offs such as between leakage and delay, and mean and variance of the leakage are discussed.
Year
DOI
Venue
2006
10.1109/ISQED.2006.83
ISQED
Keywords
Field
DocType
optimization algorithm,leakage minimization problem,physical delay model,leakage power gradient,digital circuit,gate size,circuit leakage,timing uncertainty,gate length,leakage yield,standard-cell design,discrete optimization problem,leakage optimization,sleep mode,uncertainty,threshold voltage,computer science,digital circuits,design methodology,process variation,circuits,discrete optimization,design optimization,random variables,frequency
Delay calculation,Digital electronics,Leakage (electronics),Computer science,Discrete optimization,Real-time computing,Electronic engineering,Standard cell,Electronic circuit,Threshold voltage,AND gate
Conference
ISBN
Citations 
PageRank 
0-7695-2523-7
2
0.50
References 
Authors
17
3
Name
Order
Citations
PageRank
Sarvesh Bhardwaj138622.19
Yu Cao232929.78
Sarma Vrudhula32380180.63