Name
Abstract | ||
|---|---|---|
In this paper, we examine the effectiveness of a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to store live values in the software pipelined loop while minimizing the pressure placed on architected registers. We show that decoupling the architected register space from the physical register space can greatly increase the applicability of software pipelining, even as memory latencies increase. RQs combine the major aspects of existing rotating register file and register connection techniques to generate efficient software pipeline schedules. Through the use of RQs, we can minimize the register pressure and code expansion caused by software pipelining. We demonstrate the effect of incorporating register queues and software pipelining with 983 loops taken from the Perfect Club, the SPEC suites, and the Livermore Kernels. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/12.946998 | Computers, IEEE Transactions |
Keywords | Field | DocType |
registers,indexing terms,kernel,register file,compiler,memory latency,software pipelining,vliw,computer architecture,hardware,degradation,throughput | Status register,Software pipelining,Register allocation,Computer science,Memory data register,Parallel computing,Stack register,Control register,Real-time computing,Memory address register,Processor register,Embedded system | Journal |
Volume | Issue | ISSN |
50 | 8 | 0018-9340 |
Citations | PageRank | References |
12 | 0.71 | 19 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gary S. Tyson | 1 | 571 | 49.20 |
| Mikhail Smelyanskiy | 2 | 1160 | 65.96 |
| Edward S. Davidson | 3 | 922 | 171.30 |