| Author retrospective for optimum modulo schedules for minimum register requirements | 1 | 0.37 | 2014 |
| A freespace crossbar for multi-core processors | 0 | 0.34 | 2008 |
| Probabilistic Predicate-Aware Modulo Scheduling | 3 | 0.39 | 2004 |
| A Prefetch Taxonomy | 22 | 1.03 | 2004 |
| Call Graph Prefetching for Database Applications | 18 | 1.16 | 2003 |
| Predicate-aware scheduling: a technique for reducing resource constraints | 6 | 0.73 | 2003 |
| Boosting trace cache performance with nonhead miss speculation | 1 | 0.38 | 2002 |
| Data prefetching by dependence graph precomputation | 77 | 3.12 | 2001 |
| Allocation by Conflict: A Simple, Effective Multilateral Cache Management Scheme | 0 | 0.34 | 2001 |
| Evaluating the Use of Register Queues in Software Pipelined Loops | 12 | 0.71 | 2001 |
| Branch History Guided Instruction Prefetching | 22 | 0.92 | 2001 |
| Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining | 7 | 1.05 | 2000 |
| Dual-issue scheduling with spills for binary trees | 0 | 0.34 | 1999 |
| Active Management of Data Caches by Exploiting Reuse Information | 20 | 1.53 | 1999 |
| Origin 2000 Design Enhancements for Communication Intensive Applications | 2 | 0.39 | 1998 |
| Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance | 8 | 0.88 | 1998 |
| mlcache: a flexible multi-lateral cache simulator | 13 | 1.77 | 1998 |
| Evaluating the Performance of Active Cache Management Schemes | 1 | 0.36 | 1998 |
| Utilizing reuse information in data cache management | 44 | 2.40 | 1998 |
| Configuration Independent Analysis for Characterizing Shared-Memory Applications | 12 | 1.37 | 1998 |
| Characterizing distributed shared memory performance: a case study of the Convex SPP1000 | 9 | 0.95 | 1998 |
| On high-bandwidth data cache design for multi-issue processors | 42 | 2.01 | 1997 |
| On effective data supply for multi-issue processors | 5 | 0.67 | 1997 |
| A reduced multipipeline machine description that preserves scheduling constraints | 15 | 1.53 | 1996 |
| Minimizing register requirements of a modulo schedule via optimum stage scheduling | 14 | 0.82 | 1996 |
| Performance issues in integrating temporality-based caching with prefetching | 0 | 0.34 | 1996 |
| Modeling the Communication Performance of the IBM SP2 | 25 | 2.04 | 1996 |
| Profile driven weighted decomposition | 0 | 0.34 | 1996 |
| Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design | 71 | 5.60 | 1996 |
| Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability | 1 | 0.39 | 1995 |
| The resource conflict methodology for early-stage design space exploration of superscalar RISC processors | 2 | 0.56 | 1995 |
| Optimum modulo schedules for minimum register requirements | 32 | 2.10 | 1995 |
| Register allocation for predicated code | 14 | 1.14 | 1995 |
| A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1 | 9 | 2.76 | 1994 |
| Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments | 3 | 0.84 | 1994 |
| Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs | 1 | 0.47 | 1994 |
| Optimal local register allocation for a multiple-issue machine | 2 | 0.38 | 1994 |
| Minimum register requirements for a module schedule | 26 | 1.96 | 1994 |
| Approaching a machine-application bound in delivered performance on scientific code | 15 | 2.34 | 1993 |
| Hierarchical performance modeling with MACS: a case study of the convex C-240 | 7 | 1.11 | 1993 |
| Synchronization of pipelines | 13 | 1.27 | 1993 |
| KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver | 6 | 1.10 | 1993 |
| Evaluating the communication performance of MPPs using synthetic sparse matrix multiplication workloads | 11 | 2.27 | 1993 |
| Using constraint geometry to determine maximum rate pipeline clocking | 3 | 0.65 | 1992 |
| Register requirements of pipelined processors | 31 | 2.54 | 1992 |
| A performance comparison of the IBM RS/6000 and the Astronautics ZS-1 | 18 | 2.71 | 1991 |
| The Organization Of The Cedar System | 18 | 1.51 | 1991 |
| Optimal clocking of circular pipelines | 5 | 1.29 | 1991 |
| An integrated approach to developing manufacturing control software | 4 | 0.80 | 1991 |
| An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels | 3 | 3.86 | 1988 |
