Name
Abstract | ||
|---|---|---|
Signoff timing analysis remains a critical element in the IC design flow. Multiple signoff corners, libraries, design methodologies, and implementation flows make timing closure very complex at advanced technology nodes. Design teams often wish to ensure that one tool's timing reports are neither optimistic nor pessimistic with respect to another tool's reports. The resulting “correlation” problem is highly complex because tools contain millions of lines of black-box and legacy code, licenses prevent any reverse-engineering of algorithms, and the nature of the problem is seemingly “unbounded” across possible designs, timing paths, and electrical parameters. In this work, we apply a “big-data” approach to the timer correlation problem. We develop a machine learning-based tool, Golden Timer eXtension (GTX), to correct divergence in flip-flop setup time, cell arc delay, wire delay, stage delay, and path slack at timing endpoints between timers. We propose a methodology to apply GTX to two arbitrary timers, and we evaluate scalability of GTX across multiple designs and foundry technologies / libraries, both with and without signal integrity analysis. Our experimental results show reduction in divergence between timing tools from 139.3ps to 21.1ps (i.e., 6.6×) in endpoint slack, and from 117ps to 23.8ps (4.9× reduction) in stage delay. We further demonstrate the incremental application of our methods so that models can be adapted to any outlier discrepancies when new designs are taped out in the same technology / library. Last, we demonstrate that GTX can also correlate timing reports between signoff and design implementation tools. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.273 | DATE |
Keywords | Field | DocType |
timing report,gtx,signoff timing analysis,outlier discrepancies,golden signoff timing analysis,electrical parameters,ic design flow,stage delay,signal integrity analysis,timer correlation problem,design implementation tool,golden signoff timing,learning (artificial intelligence),endpoint slack,deep learning methodology,big-data approach,machine learning-based tool,timing paths,timing endpoint,foundry technology-libraries,delays,time 139.3 ps to 21.1 ps,path slack,golden timer extension,advanced technology nodes,timing tool,timing path,flip-flops,big data,design methodology,flip-flop setup time,cell arc delay,wire delay,learning artificial intelligence,silicon | Signoff,Computer science,Real-time computing,Integrated circuit design,Static timing analysis,Legacy code,Timer,Big data,Timing closure,Scalability | Conference |
ISSN | Citations | PageRank |
1530-1591 | 7 | 0.60 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seung-Soo Han | 1 | 66 | 16.00 |
| Andrew B. Kahng | 2 | 7582 | 859.06 |
| Siddhartha Nath | 3 | 240 | 15.01 |
| Ashok S. Vydyanathan | 4 | 7 | 0.60 |