Paper Info
Title
Securing Scan Design Using Lock and Key Technique
Abstract
Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip [1]. In order to defend from scan based attacks, we present the Lock & Key technique. Our proposed technique provides security while not negatively impacting the design驴s fault coverage. This technique requires only that a small area overhead penalty is incurred for a significant return in security. Lock & Key divides the already present scan chain into smaller subchains of equal length that are controlled by an internal test security controller. When a malicious user attempts to manipulate the scan chain, the test security controller goes into insecure mode and enables each subchain in an unpredictable sequence making controllability and observability of the circuit under test very difficult. We will present and analyze the design of the Lock & Key technique to show that this is a flexible option to secure scan designs for various levels of security.
Year
DOI
Venue
2005
10.1109/DFTVS.2005.58
DFT
Keywords
Field
DocType
high controllability,key technique,flexible option,test security controller,internal test security controller,intellectual property,proposed technique,security threat,insecure mode,equal length,securing scan design,security,fault coverage,scan chain,integrated circuit design,vlsi design,chip
Control theory,Observability,Controllability,Fault coverage,Lock (computer science),Computer science,Scan chain,Electronic engineering,Integrated circuit design,Very-large-scale integration,Embedded system
Conference
ISSN
ISBN
Citations 
1550-5774
0-7695-2464-8
27
PageRank 
References 
Authors
2.29
15
4
Name
Order
Citations
PageRank
Jeremy Lee1684.54
Mohammed Tehranipoor2272.29
Chintan Patel338537.44
Jim Plusquellic454653.16