Name
Title | ||
|---|---|---|
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations |
Abstract | ||
|---|---|---|
The control of leakage power consumption is a growing design challenge for current and future CMOS circuits. Among existing techniques, 'parking' a circuit in a minimum leakage state during its standby mode of operation requires minimal circuit modification and results in significant leakage reduction. In this paper we present a heuristic approach (referred to as MLVC) to determine the input vector which minimizes leakage for a combinational design. This approach utilizes approximate signal probabilities of internal nodes to aid in finding the minimum leakage vector. We utilize a probabilistic heuristic to select the next gate to be processed as well as to select the best state of the selected gate. A fast SAT solver is employed to ensure the consistency of the assignments that are made in this process. A variant of MLVC, referred to as MLVC-VAR, is also presented. MLVC-VAR includes the effect of random variations in leakage values due to process, voltage and temperature (PVT) variations. Including the effect of PVT variations for determining minimum leakage vector is crucial because leakage currents have an exponential dependence on power supply, threshold voltage and temperature. To the best of the authors' knowledge, no other minimum leakage vector determination work has to date included the effect of PVT variations. Experimental results indicate that our MLVC method has very low runtimes, with excellent accuracy compared to existing approaches. Further, the comparison of the mean and standard deviation of the circuit leakage values for MLVC with MLVC-VAR and an existing random vector generating approach proves the need for considering these variations while determining the minimum leakage vector. MLVC-VAR reports, on average, about 9.69% improvement over MLVC with similar runtimes and 5.98% improvement over the random vector generation approach with significantly lower runtimes. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1016/j.vlsi.2007.10.001 | Integration |
Keywords | Field | DocType |
circuit leakage value,leakage value,leakage power consumption,minimum leakage state,minimum leakage vector determination,existing random vector generating,combinational design,probabilistic method,random pvt variation,leakage current,significant leakage reduction,pvt variation,minimum leakage vector,sat solver,standard deviation,subthreshold leakage,threshold voltage | Standby power,Leakage (electronics),Computer science,Electronic engineering,CMOS,Multivariate random variable,Subthreshold conduction,Probabilistic logic,Electronic circuit,Threshold voltage | Journal |
Volume | Issue | ISSN |
41 | 3 | Integration, the VLSI Journal |
Citations | PageRank | References |
7 | 0.56 | 30 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanupriya Gulati | 1 | 196 | 16.53 |
| Nikhil Jayakumar | 2 | 215 | 20.42 |
| Sunil P. Khatri | 3 | 1213 | 137.09 |
| D. M. H. Walker | 4 | 327 | 31.15 |