Title
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults.
Abstract
This work proposes a novel built-in current sensor for detecting transient faults of short and long duration as well as multiple faults in combinational and sequential logic. Unlike prior similar strategies, which are formed by pairs of PMOS and NMOS sensors, the proposed scheme is a single sensor connected to PMOS and NMOS bulks of the monitored logic. In comparison with existing transient-fault mitigation techniques, the paper presents very competitive results that indicate no performance penalty, and overheads of only 26 % in power consumption and 23 % in area.
Year
DOI
Venue
2013
10.1109/PATMOS.2013.6662169
PATMOS
Keywords
Field
DocType
fault tolerance,security,combinational circuits,sequential circuits
Sequential logic,NMOS logic,Computer science,Combinational logic,CMOS,Electronic engineering,Real-time computing,Fault tolerance,Current sensor,PMOS logic,Pull-up
Conference
ISSN
Citations 
PageRank 
2474-5456
3
0.41
References 
Authors
11
6
Name
Order
Citations
PageRank
Rodrigo Possamai Bastos18013.80
Frank Sill Torres27014.65
Jean-Max Dutertre331329.14
Marie-Lise Flottes436645.31
Giorgio Di Natale536854.26
Bruno Rouzeyre645649.44