Title
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Abstract
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV i...
Year
DOI
Venue
2010
10.1109/JSSC.2009.2034414
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Random access memory,Ferroelectric films,Nonvolatile memory,Parasitic capacitance,Clocks,CMOS process,Bandwidth,SDRAM,Current supplies,Timing
Dynamic random-access memory,Dram,Capacitance,Parasitic capacitance,Octal,Computer science,Electronic engineering,CMOS,Non-volatile memory,Ferroelectric RAM,Electrical engineering
Journal
Volume
Issue
ISSN
45
1
0018-9200
Citations 
PageRank 
References 
23
3.30
6
Authors
33