Author Info
Name
Affiliation
Papers
HIDEHIRO SHIGA
Toshiba Corp. Semicond. Co., Yokohama, Japan
4
Collaborators
Citations 
PageRank 
68
41
15.51
Referers 
Referees 
References 
241
50
12
Search Limit
100241
Title
Citations
PageRank
Year
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs00.342015
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes233.302010
A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput910.182007
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode91.702006