Paper Info
Title
Synthesis of networks on chips for 3D systems on chips
Abstract
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Designing power efficient NoCs for 3D SoCs that satisfy the application performance requirements, while satisfying the 3D technology constraints is a big challenge. In this work, we address this problem and present a synthesis approach for designing power-performance efficient 3D NoCs. We present methods to determine the best topology, compute paths and perform placement of the NoC components in each 3D layer. We perform experiments on varied, realistic SoC benchmarks to validate the methods and also perform a comparative study of the resulting 3D NoC designs with 3D optimized mesh topologies. The NoCs designed by our synthesis method results in large interconnect power reduction (average of 38%) and latency reduction (average of 25%) when compared to traditional NoC designs.
Year
DOI
Venue
2009
10.1109/ASPDAC.2009.4796487
Yokohama
Keywords
Field
DocType
design complexity,noc component,power efficient nocs,power reduction,traditional noc design,present method,latency reduction,synthesis approach,synthesis method result,noc design,topology,bandwidth,satisfiability,system on chip,network on chip,network topology,3d,three dimensional,integrated circuit design,benchmark testing,power efficiency,stacking,system on a chip
System on a chip,Computer science,Latency (engineering),Network on a chip,Network topology,Electronic engineering,Integrated circuit design,Bandwidth (signal processing),Interconnection,Benchmark (computing),Embedded system
Conference
ISSN
ISBN
Citations 
2153-6961
978-1-4244-2749-9
50
PageRank 
References 
Authors
1.61
28
4
Name
Order
Citations
PageRank
Srinivasan Murali1215596.64
Ciprian Seiculescu22199.26
Luca Benini3131161188.49
Giovanni De Micheli4102451018.13