Paper Info
Title
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
Abstract
Video signal processing requires complex algorithms performing many basic operations on a video stream. To perform these calculations in real-time in a FPGA, we must use innovative structures to meet speed requirements while managing complexity. As part of a project aiming at the development of a video noise reducer, we developed an optimized processing stream that required some floating-point calculations. This paper presents the rationale for developing a floating-point unit, justifies the data representation used, its implementation in a Xilinx VirtexE FPGA and reports the performance we obtained. A divider using this representation is also presented, with its implementation and performances in the same FPGA.
Year
DOI
Venue
2002
10.1145/503048.503056
FPGA
Keywords
Field
DocType
hardware division,floating-point,flexible floating-point format,floating-point unit,xilinx virtexe fpga,basic operation,hyardware optimization,complex algorithm,optimizing data-paths,data-path optimization,video-processing,floating-point/fixed-point conversion,floating-point calculation,video stream,video signal processing,optimized processing stream,fpga,data representation,video noise reducer,fixed point,floating point unit,video processing,real time,floating point
Signal processing,Floating point,Noise (video),Computer science,Real-time computing,Reducer,Computer hardware,Video processing,External Data Representation,Parallel computing,Double-precision floating-point format,Field-programmable gate array,Embedded system
Conference
ISBN
Citations 
PageRank 
1-58113-452-5
22
4.26
References 
Authors
4
6
Name
Order
Citations
PageRank
J. Dido1224.26
N. Geraudie2224.26
L. Loiseau3224.26
O. Payeur4224.26
Y. Savaria511926.71
D. Poirier6224.26