Paper Info
Title
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Abstract
Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor manufacturers. Regarding the NoC, variability causes that the delays of links and routers do not match those initially established at design time. In this paper we analyze how variability affects the NoC by applying a new variability model to 100 instances of an 8 x 8 mesh NoC synthesized using 45 nm technology. We also show that GALS-based NoCs present communication bottlenecks due to the slower components of the network, which cause congestion, thus reducing performance. This performance reduction finally affects the applications being executed in the CMP because they may be mapped to slower areas of the chip. In this paper we show that using a mapping algorithm that considers variability data may improve application execution time up to 50%.
Year
DOI
Venue
2011
10.1016/j.jpdc.2010.09.006
J. Parallel Distrib. Comput.
Keywords
Field
DocType
performance reduction,slower component,process variation,noc (or network-on-chip),chip multiprocessors,variability data,variability cause,design time,process mapping,process variations,application execution time,router design,slower area,new burden,cmp (or chip multiprocessor),nm noc-based cmps,new variability model,network on chip,chip
Bottleneck,System on a chip,Globally asynchronous locally synchronous,Computer science,Parallel computing,Multiprocessing,Process variation,Router,Very-large-scale integration,Multi-core processor,Embedded system,Distributed computing
Journal
Volume
Issue
ISSN
71
5
Journal of Parallel and Distributed Computing
Citations 
PageRank 
References 
4
0.41
26
Authors
5
Name
Order
Citations
PageRank
Carles HernáNdez117626.56
Antoni Roca21408.51
J. Flich377552.09
F. Silla417316.36
J. Duato582974.13