Name
Title | ||
|---|---|---|
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISSCC.2012.6176993 | international solid-state circuits conference |
Keywords | Field | DocType |
phase locked loops,high resolution,chip,jitter,phase noise,oscillations,phase lock loop,limit cycle,analog circuits,power dissipation,quantization error,bandwidth | Phase-locked loop,Computer science,Oscillator phase noise,Phase noise,Electronic engineering,DPLL algorithm,Bandwidth (signal processing),Digital clock,Jitter,Quantization (signal processing),Electrical engineering | Conference |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amr Elshazly | 1 | 242 | 28.08 |
| Rajesh Inti | 2 | 118 | 13.20 |
| Brian Young | 3 | 118 | 12.20 |
| Pavan Kumar Hanumolu | 4 | 554 | 84.82 |