Name
Title | ||
|---|---|---|
A Novel Scan Segmentation Design Method For Avoiding Shift Timing Failure In Scan Testing |
Abstract | ||
|---|---|---|
High power consumption in scan testing can cause undue yield loss which has increasingly become a serious problem for deep-submicron VLSI circuits. Growing evidence attributes this problem to shift timing failures, which are primarily caused by excessive switching activity in the proximities of clock paths that tends to introduce severe clock skew due to IR-drop-induced delay increase. This paper is the first of its kind to address this critical issue with a novel layout-aware scheme based on scan segmentation design, called LCTI-SS (Low-Clock-Tree-Impact Scan Segmentation). An optimal combination of scan segments is identified for simultaneous clocking so that the switching activity in the proximities of clock trees is reduced while maintaining the average power reduction effect on conventional scan segmentation. Experimental results on benchmark and industrial circuits have demonstrated the advantage of the LCTI-SS scheme. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TEST.2011.6139162 | 2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC) |
Keywords | Field | DocType |
scan testing, shift power reduction, scan segmentation, switching activity, clock tree, clock skew | Timing failure,Logic gate,Segmentation,Computer science,Scan chain,Real-time computing,Electronic engineering,Integrated circuit design,Clock skew,Electronic circuit,Very-large-scale integration | Conference |
ISSN | Citations | PageRank |
1089-3539 | 8 | 0.49 |
References | Authors | |
21 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuta Yamato | 1 | 138 | 9.45 |
| Xiaoqing Wen | 2 | 790 | 77.12 |
| Michael A. Kochte | 3 | 276 | 27.23 |
| Kohei Miyase | 4 | 562 | 38.71 |
| Seiji Kajihara | 5 | 989 | 73.60 |
| Laung-terng Wang | 6 | 601 | 44.22 |