Name
Abstract | ||
|---|---|---|
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we extend these schemes to achieve this conflict-free access for a larger number of strides. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. Both matched and unmatched memories are considered: we show that the number of strides is even larger for the latter case. The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1145/139669.140400 | ISCA |
Keywords | Field | DocType |
registers,bandwidth,linear transformation,machinery,access control,hardware,distributed computing,throughput,vector processor,out of order | Permission,Computer science,Parallel computing,Real-time computing,Bandwidth (signal processing),Linear map,Access control,Throughput,Out-of-order execution | Conference |
Volume | Issue | ISBN |
20 | 2 | 0-89791-509-7 |
Citations | PageRank | References |
40 | 5.99 | 13 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mateo Valero | 1 | 4520 | 355.94 |
| Tomás Lang | 2 | 417 | 73.70 |
| José M. Llabería | 3 | 104 | 15.90 |
| Montse Peiron | 4 | 82 | 10.76 |
| Eduard Ayguadé | 5 | 2406 | 216.00 |
| Juan J. Navarro | 6 | 323 | 42.90 |
| J NavarraJuan | 7 | 40 | 5.99 |