Name
Abstract | ||
|---|---|---|
A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 Vt 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 5... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/JSSC.2007.909336 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Viterbi algorithm,Circuits,Maximum likelihood decoding,CMOS technology,Power measurement,Read-write memory,Signal processing algorithms,Convolutional codes,Throughput,Power generation | Signal processing,Convolutional code,Computer science,CMOS,Electronic engineering,Viterbi decoder,Transistor,Electronic circuit,Viterbi algorithm,Scalability | Journal |
Volume | Issue | ISSN |
43 | 1 | 0018-9200 |
Citations | PageRank | References |
9 | 0.64 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mark A. Anders | 1 | 185 | 17.43 |
| S. Mathew | 2 | 462 | 76.59 |
| S. K. Hsu | 3 | 521 | 52.06 |
| Ram Krishnamurthy | 4 | 650 | 74.63 |
| Shekhar Borkar | 5 | 4236 | 494.95 |