| Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS | 0 | 0.34 | 2020 |
| Reliability and Performance Issues in SiC MOSFETs: Insight Provided by Spin Dependent Recombination | 0 | 0.34 | 2019 |
| Ultra-Lightweight 548–1080 Gate 166Gbps/W–12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS | 0 | 0.34 | 2018 |
| A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS | 0 | 0.34 | 2018 |
| A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS | 0 | 0.34 | 2016 |
| 250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. | 0 | 0.34 | 2016 |
| 16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS | 21 | 0.96 | 2014 |
| 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS | 42 | 2.60 | 2014 |
| A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS | 0 | 0.34 | 2012 |
| 3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS | 1 | 0.35 | 2010 |
| 18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS | 5 | 0.55 | 2010 |
| A 320 Mv 56 Mu W 411 Gops/Watt Ultra-Low Voltage Motion Estimation Accelerator In 65 Nm Cmos | 19 | 2.98 | 2009 |
| A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS | 9 | 0.64 | 2008 |
| A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit | 5 | 0.56 | 2007 |
| An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS | 0 | 0.34 | 2006 |
| A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core | 4 | 0.96 | 2006 |
| Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses | 7 | 0.58 | 2005 |
| An Improved Unified Scalable Radix-2 Montgomery Multiplier | 48 | 2.52 | 2005 |
| Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends | 24 | 2.01 | 2001 |
