Name
Title | ||
|---|---|---|
QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores |
Abstract | ||
|---|---|---|
Transistor density continues to increase exponentially, but power dissipation per transistor is improving only slightly with each generation of Moore's law. Given the constant chip-level power budgets, this exponentially decreases the percentage of transistors that can switch at full frequency with each technology generation. Hence, while the transistor budget continues to increase exponentially, the power budget has become the dominant limiting factor in processor design. In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve system performance. To trade transistors for energy efficiency in a scalable manner, we propose Quasi-specific Cores, or QsCores, specialized processors capable of executing multiple general-purpose computations while providing an order of magnitude more energy efficiency than a general-purpose processor. The QsCores design flow is based on the insight that similar code patterns exist within and across applications. Our approach exploits these similar code patterns to ensure that a small set of specialized cores support a large number of commonly used computations. We evaluate QsCores's ability to target both a single application library (e.g., data structures) as well as a diverse workload consisting of applications selected from different domains (e.g., SPECINT, EEMBC, and Vision). Our results show that QsCores can provide 18.4 x better energy efficiency than general-purpose processors while reducing the amount of specialized logic required to support the workload by up to 66%. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2155620.2155640 | MICRO |
Keywords | Field | DocType |
scalable energy efficiency,quasi-specific core,dark silicon,specialized processor,multiple general-purpose computation,general-purpose processor,specialized core,similar code pattern,constant chip-level power budget,qscores design flow,better energy efficiency,specialized logic,energy efficiency,energy efficient,merging | Dark silicon,Power budget,Computer science,Efficient energy use,Parallel computing,Real-time computing,Design flow,Processor design,SPECint,Transistor,Scalability | Conference |
ISSN | ISBN | Citations |
1072-4451 | 978-1-5090-6605-6 | 64 |
PageRank | References | Authors |
2.77 | 21 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ganesh Venkatesh | 1 | 274 | 17.97 |
| Jack Sampson | 2 | 398 | 32.45 |
| Nathan Goulding-Hotta | 3 | 163 | 10.26 |
| Sravanthi Kota Venkata | 4 | 152 | 6.12 |
| Michael Bedford Taylor | 5 | 1707 | 154.51 |
| Steven Swanson | 6 | 1434 | 82.33 |