Paper Info
Title
Two-level hierarchical register file organization for VLIW processors
Abstract
High-performance microprocessors are currently de- signed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register re- quirements of the loops. If more registers than those avail- able in the architecture are required, some actions (such as spill code insertion) have to be applied to reduce this pres- sure, at the expense of some performance degradation. This degradation could be avoided if a high-capacity register file were included without causing a negative impact on the cycle time of the processor. In this paper we propose a two-level hierarchical regis- ter file organization for VLIW architectures that combines high capacity and low access time. For the configuration proposed in this paper, the new organization achieves a speed-up of 10-14% over a monolithic organization with 64 registers; it is obtained with a 43% (40%) reduction in area (peak power dissipation). Compared to a monolithic file with 32 registers, the speed-up is as much as 38% with just a 14% (4%) increase in area (peak power dissipation).
Year
DOI
Venue
2000
10.1145/360128.360143
MICRO
Keywords
Field
DocType
two-level hierarchical register file,vliw processor,vliw,cycle time,parallel processing,speed up,instruction level parallelism,instruction sets,register file,degradation,registers,power dissipation,dynamic scheduling
Instruction-level parallelism,Access time,Instruction register,Computer science,Very long instruction word,Scheduling (computing),Instruction set,Parallel computing,Register file,Real-time computing,Processor register
Conference
ISSN
ISBN
Citations 
1072-4451
1-58113-196-8
47
PageRank 
References 
Authors
3.58
21
4
Name
Order
Citations
PageRank
Javier Zalamea11388.87
Josep Llosa257439.30
Eduard Ayguadé32406216.00
Mateo Valero44520355.94