Name
Abstract | ||
|---|---|---|
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISQED.2009.4810372 | San Jose, CA |
Keywords | Field | DocType |
cell area,margin degradation,sram cell,low voltage operation,minimum operating voltage,proposed 128-kb sram,selection problem,cell current,column line,faster access time,low voltage,probability density function,layout,logic,transistors,sram,degradation,data mining,low power electronics,leakage current,topology,threshold voltage | Leakage (electronics),Access time,Computer science,Static random-access memory,Real-time computing,Electronic engineering,Sram cell,Low voltage,Transistor,Low-power electronics,Operating voltage | Conference |
ISBN | Citations | PageRank |
978-1-4244-2953-0 | 7 | 0.65 |
References | Authors | |
5 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shunsuke Okumura | 1 | 63 | 12.54 |
| Yusuke Iguchi | 2 | 56 | 6.38 |
| Shusuke Yoshimoto | 3 | 30 | 12.56 |
| Hidehiro Fujiwara | 4 | 72 | 12.67 |
| Hiroki Noguchi | 5 | 145 | 20.04 |
| Koji Nii | 6 | 223 | 44.78 |
| Hiroshi Kawaguchi | 7 | 395 | 91.51 |
| Masahiko Yoshimoto | 8 | 7 | 0.65 |