Name
Abstract | ||
|---|---|---|
Given the logic density of modern FPGAs, it is feasible to use FPGAs for floating-point applications. However, it is important that any floating-point units that are used be highly optimized. This paper introduces an open source library of highly optimized floating-point units for Xilinx FPGAs. The units are fully IEEE compliant and acheive approximately 230 MHz operation frequency for doubleprecision add and multiply in a Xilinx Virtex-2-Pro FPGA (-7 speed grade). This speed is acheived with a 10 stage adder pipeline and a 12 stage multiplier pipeline. The area requirement is 571 slices for the adder and 905 slices for the multiplier. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/FCCM.2006.54 | Napa, CA |
Keywords | Field | DocType |
xilinx virtex-2-pro fpga,modern fpgas,floating-point application,floating-point unit,open source high performance,ieee compliant,stage adder pipeline,mhz operation frequency,speed grade,stage multiplier pipeline,floating-point modules,xilinx fpgas,kernel,ieee floating point,logic,floating point arithmetic,frequency,adders,field programmable gate arrays,floating point unit,floating point,reconfigurable computing,fpga | Kernel (linear algebra),Adder,Computer science,Floating point,Parallel computing,Field-programmable gate array,Multiplier (economics),Computer hardware,IEEE floating point,Reconfigurable computing | Conference |
ISBN | Citations | PageRank |
0-7695-2661-6 | 14 | 1.09 |
References | Authors | |
6 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. Scott Hemmert | 1 | 577 | 50.62 |
| Keith D. Underwood | 2 | 847 | 77.39 |