Name
Abstract | ||
|---|---|---|
This paper presents a technique to correct multiple logic design errors in a gate-level netlist. A number of methods have been proposed for correcting single logic design errors. However, the extension of these methods to more than one error is still very limited. We direct our attention to circuits with a low multiplicity of errors. By assuming different error dependency scenarios, multiple errors are corrected by repeatedly applying a single error search and correction algorithm. Experimental results on correcting double-design errors and triple-design errors on ISCAS and MCNC benchmark circuits are included. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/92.585227 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
single error search,triple-design error,digital circuit,correction algorithm,double-design error,mcnc benchmark circuit,single logic design error,different error dependency scenario,multiple logic design error,multiple error,error correction,digital circuits,boolean functions,integrated circuit design,very large scale integration,process design,diagnosis,logic design,vlsi,debugging,indexing terms | Logic synthesis,Boolean function,Netlist,Digital electronics,Computer science,Algorithm,Error detection and correction,Electronic engineering,Integrated circuit design,Very-large-scale integration,Integrated circuit | Journal |
Volume | Issue | ISSN |
5 | 2 | 1063-8210 |
Citations | PageRank | References |
21 | 1.47 | 11 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pi-yu Chung | 1 | 217 | 22.08 |
| Ibrahim N. Hajj | 2 | 572 | 79.52 |