Paper Info
Title
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
Abstract
High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.
Year
DOI
Venue
2012
10.1145/2228360.2228406
DAC
Keywords
Field
DocType
cmp,stt-ram,enhanced performance,spin-transfer-torque-ram,data-retention-time,cache revive,cache storage,sram chips,heterogeneous (hybrid) systems,volatile stt-ram cache,volatile stt-ram caches,nonvolatility property,sram,write-latency,energy consumption,optimal retention-time,multicore system,universal memory replacement,switches,current density,stt ram,radiation detectors,system on a chip,hybrid system,retention time
System on a chip,Cache,Computer science,Latency (engineering),High density,Static random-access memory,Universal memory,Real-time computing,Low leakage,Energy consumption
Conference
ISSN
ISBN
Citations 
0738-100X
978-1-4503-1199-1
120
PageRank 
References 
Authors
3.38
16
7
Search Limit
100120
Name
Order
Citations
PageRank
Adwait Jog156823.32
Asit K. Mishra2121646.21
Cong Xu3115448.25
Yuan Xie46430407.00
Narayanan Vijaykrishnan56955524.60
Ravishankar K. Iyer63489504.32
Chita R. Das7104645.21