Name
Abstract | ||
|---|---|---|
This paper describes multigrain parallel processing on a compiler cooperative chip multiprocessor. The multigrain parallel processing hierarchically exploits multiple grains of parallelism such as coarse grain task parallelism, loop iteration level parallelism and statement level near-fine grain parallelism. The chip multiprocessor has been designed to attain high effective performance, cost effectiveness and high software productivity by supporting the optimizations of the multigrain parallelizing compiler, which is developed by Japanese Millennium Project IT21 "Advance Parallelizing Compiler". To achieve full potential of multigrain parallel processing, the chip multiprocessor integrates simple single-issue processors having distributed shared data memory for both optimal use of data locality and scalar data transfer, local data memory for processor private data, in addition to centralized shared memory for shared data among processors. This paper focuses on the scalability of the chip multiprocessor having up to eight processors on a chip by exploiting of the multigrain parallelism from SPECfp95 programs. When microSPARC like the simple processor core is used under assumption of 90 nm technology and 2.8 GHz, the evaluation results show the speedups for eight processors and four processors reach 7.1 and 3.9, respectively. Similarly, when 400 MHz is assumed for embedded usage, the speedups reach 7.8 and 4.0, respectively. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/INTERACT.2005.9 | Interaction between Compilers and Computer Architectures |
Keywords | Field | DocType |
multigrain parallel processing,distributed shared memory systems,microprocessor chips,parallel programming,compiler cooperative chip multiprocessor,parallel architectures,speculative thread,specfp95 program,system-on-chip,parallelizing compiler,optimization,parallelising compilers,trace-level speculation,distributed shared data memory,optimising compilers,trace-level speculative multithreaded processors,system on chip,shared memory,parallel processing,chip,cost effectiveness,data transfer | Computer architecture,System on a chip,Shared memory,Computer science,Task parallelism,Parallel computing,Distributed memory,Compiler,Multiprocessing,Data parallelism,Multi-core processor | Conference |
ISSN | ISBN | Citations |
1550-6207 | 0-7695-2321-8 | 11 |
PageRank | References | Authors |
1.61 | 9 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keiji Kimura | 1 | 120 | 23.20 |
| Yasutaka Wada | 2 | 72 | 11.19 |
| Hirufumi Nakano | 3 | 11 | 1.61 |
| Takeshi Kodaka | 4 | 16 | 3.07 |
| Jun Shirako | 5 | 433 | 34.56 |
| Kazuhisa Ishizaka | 6 | 74 | 7.23 |
| Hironori Kasahara | 7 | 285 | 44.35 |