Title
A Hybrid FPGA Model to Estimate On-Chip Crossbar Logic Utilization in SoC Platforms
Abstract
FPGA analytical models, that express the relationship between architectural parameters (e.g., LUT size, cluster size, inputs per cluster, etc) and performance (e.g., logic utilization, critical path delay, power, etc), have been designed mainly for island-style FPGAs targeting a general application. Therefore, most analytical models will produce inaccurate results when heterogeneous FPGA architectures are targeted. Furthermore, the inherent continuous nature of mathematical models also prevent them from capturing the discrete effects of uniform circuits. Example of such circuits are crossbar switches and barrel shifters. In this paper, we derive a biased model that captures the discrete effects with respect to the logic utilization of crossbar switches by varying the LUT size.
Year
DOI
Venue
2013
10.1109/IPDPSW.2013.138
IPDPS Workshops
Keywords
Field
DocType
analytical model,heterogeneous fpga architecture,lut size,architectural parameter,soc platforms,discrete effect,crossbar switch,estimate on-chip crossbar logic,barrel shifters,logic utilization,hybrid fpga model,cluster size,fpga analytical model,mathematical models,switches,system on chip,multiplexing,computer architecture,mathematical model,field programmable gate arrays
Lookup table,System on a chip,Computer science,Programmable logic array,Field-programmable gate array,Critical path delay,Computer hardware,Electronic circuit,Mathematical model,Crossbar switch,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
0
Authors
2
Name
Order
Citations
PageRank
Yoon Kah Leow132.10
Ali Akoglu215729.40