Name
Abstract | ||
|---|---|---|
There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for today's high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TEST.2010.5699203 | ITC |
Keywords | Field | DocType |
design for test,logic gates,design for testability,process variation | Power budget,Design for testing,Logic gate,Resistive touchscreen,Computer science,Crosstalk,Microprocessor,Electronic engineering,Computer hardware,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-4244-7206-2 | 5 |
PageRank | References | Authors |
0.77 | 18 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahmut Yilmaz | 1 | 189 | 13.84 |
| Baosheng Wang | 2 | 169 | 18.08 |
| Jayalakshmi Rajaraman | 3 | 6 | 1.22 |
| Tom Olsen | 4 | 5 | 0.77 |
| Kanwaldeep Sobti | 5 | 51 | 4.23 |
| Dwight Elvey | 6 | 5 | 0.77 |
| Jeff Fitzgerald | 7 | 27 | 2.55 |
| Grady Giles | 8 | 84 | 18.85 |
| Wei-Yu Chen | 9 | 5 | 0.77 |