| Accurate Area, Time and Power Models for FPGA-Based Implementations | 14 | 0.89 | 2011 |
| Structural Tests Of Slave Clock Gating In Low-Power Flip-Flop | 1 | 0.45 | 2011 |
| The scan-DFT features of AMD's next-generation microprocessor core. | 5 | 0.77 | 2010 |
| Accurate models for estimating area and power of FPGA implementations | 19 | 0.96 | 2008 |
| Efficient Function Evaluations With Lookup Tables For Structured Matrix Operations | 5 | 0.56 | 2007 |
| Geometric Tiling For Reducing Power Consumption In Structured Matrix Operations | 7 | 0.61 | 2006 |
