Name
Abstract | ||
|---|---|---|
In designs using DFT, such as scan, some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause nonfunctional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudofunctional. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DFTVS.2005.49 | DFT |
Keywords | Field | DocType |
supply current,integrated circuit testing,dft insertion,illegal state,unreachable state,atpg testing,pseudofunctional delay fault test generation,automatic test pattern generation,normal power dissipation,non-functional operation,discrete fourier transforms,fault diagnosis,scan designs,generating pseudo-functional delay fault,new technique,circuit testing,logic testing,power dissipation | Stuck-at fault,Boundary scan,Automatic test pattern generation,Fault coverage,Computer science,Dissipation,Scan chain,Real-time computing,Electronic engineering,Electronic circuit,Test compression | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-2464-8 | 51 |
PageRank | References | Authors |
2.18 | 17 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhuo Zhang | 1 | 70 | 3.49 |
| Sudhakar M. Reddy | 2 | 5747 | 699.51 |
| Irith Pomeranz | 3 | 3829 | 336.84 |