Paper Info
Title
Locality-Aware Process Scheduling for Embedded MPSoCs
Abstract
Utilizing on-chip caches in embedded multiprocessor-system-on-a-chip (MPSoC) basedsystems is critical from both performance and power perspectives. While most of the prior work that targets at optimizing cache behavior are performed at hardware and compilation levels, operating system (OS) can also play major role as it sees the global access pattern information across applications. This paper proposes a cache-conscious OS process scheduling strategy based on data reuse. The proposed scheduler implements two complementary approaches. First, the processes that do not share any data between them are scheduled at different cores if it is possible to do so. Second, the processes that could not be executed at the same time (due to dependences) but share data among each other are mapped to the same processor core so that they share the cache contents. Our experimental results using this new data locality aware OS scheduling strategy are promising, and show significant improvements in task completion times.
Year
DOI
Venue
2005
10.1109/DATE.2005.198
Computing Research Repository
Keywords
Field
DocType
on-chip cache,cache behavior,complementary approach,cache-conscious os process scheduling,cache content,data reuse,compilation level,new data,aware os scheduling strategy,share data,system on a chip,embedded systems,operating system,system on chip,chip,computer science,spc,hardware,performance,degradation,process scheduling,communication networks,network on a chip,operating systems
Locality,System on a chip,Telecommunications network,Cache,Computer science,Scheduling (computing),Parallel computing,Network on a chip,Real-time computing,MPSoC,Multi-core processor,Embedded system
Conference
Volume
ISSN
ISBN
abs/0710.4
Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
0-7695-2288-2
Citations 
PageRank 
References 
14
1.21
6
Authors
2
Name
Order
Citations
PageRank
Mahmut T. Kandemir17371568.54
Guilin Chen29210.54