Name
Abstract | ||
|---|---|---|
This paper describes a method for the diagnosis and correction of logic design errors in an erroneous gate-level implementation. Our method is robust and covers more types of design errors than previous work. Our major contribution is providing significant improvement in efficiency, which is most crucial for practical applications. The notion of immediate dominator set is introduced for efficient error diagnosis. Implicit enumeration of the function space is developed for achieving fast error correction. Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques. Circuits with thousands of gates can be corrected in minutes. |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/DAC.1993.204000 | DAC |
Keywords | Field | DocType |
digital circuit,logic design error,logic circuits,function space,error correction,dominating set,robustness,differential equations,digital circuits,logic design | Logic synthesis,Digital electronics,Sequential logic,Computer science,Logic optimization,Algorithm,Electronic engineering,Error detection and correction,Logic family,Register-transfer level,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-89791-577-1 | 40 |
PageRank | References | Authors |
3.29 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pi-yu Chung | 1 | 217 | 22.08 |
| Yi-min Wang | 2 | 3573 | 274.00 |
| Ibrahim N. Hajj | 3 | 572 | 79.52 |