Paper Info
Title
EDT bandwidth management - Practical scenarios for large SoC designs
Abstract
The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.
Year
DOI
Venue
2013
10.1109/TEST.2013.6651898
ITC
Keywords
Field
DocType
large industrial system-on-chip designs,edt bandwidth management,processor scheduling,preemptive test scheduling,integrated circuit testing,data compression,system-on-chip,channel bandwidth management methodology,test logic architectures,integrated circuit design,soc test scheduling algorithms,embedded deterministic test environment,large soc designs,scan data volume,embedded test data compression,soc pin allocation,system on chip
System on a chip,Computer science,Test scheduling,Real-time computing,Electronic engineering,Test data compression,Integrated circuit design,Electronic circuit,Data compression,Channel capacity,Bandwidth management
Conference
ISSN
Citations 
PageRank 
1089-3539
8
0.58
References 
Authors
29
9
Name
Order
Citations
PageRank
Jakub Janicki1464.31
Jerzy Tyszer283874.98
W.-T. Cheng380.58
Yi Huang485098.48
Mark Kassab565448.74
Nilanjan Mukherjee680157.26
Janusz Rajski72460201.28
Y. Dong880.58
G. Giles980.58