Paper Info
Title
High level architectural synthesis: precedence analysis and automatic cycle detection in data flow graphs
Abstract
In this paper a low complexity procedure for precedence analysis and cycle detection in DFGs, representing abstract architectures during the high level synthesis process, is presented. The proposed approach aims to reduce the computational overhead required to take topological constraints into consideration during the scheduling process.
Year
DOI
Venue
1994
10.1016/0165-6074(94)90020-5
Microprocessing and Microprogramming
Keywords
DocType
Volume
precedence analysis,data flow graph,automatic cycle detection,high level,architectural synthesis
Journal
40
Issue
ISSN
Citations 
10
Microprocessing and Microprogramming
0
PageRank 
References 
Authors
0.34
2
3
Name
Order
Citations
PageRank
Anna Antola1588.33
Fausto Distante242.33
Andrea Marchese321.51