Name
Abstract | ||
|---|---|---|
This paper presents the design and implementation of a 16 X 16 bit array multiplier with real-time self checking capabilities. The multiplier operates on two's complement data and outputs the full 31-bit result using the modified Booth's algorithm for multiplication. An error detection flag during each multiplication operation indicates the presence or absence of a fault in the multiplier circuit. The circuit is designed using Differential Cascode Voltage Switch (DCVS) logic and is implemented in 2mu CMOS technology with double metal interconnects. The simulated multiplication throughput of the circuit is 26 MHz and its power dissipation 200 mW. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1016/0167-9260(92)90027-V | INTEGRATION-THE VLSI JOURNAL |
Keywords | Field | DocType |
MULTIPLIER, SELF-CHECKING, DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC, ONLINE ERROR DETECTION | Logic gate,Cascode,Computer science,16-bit,Circuit design,Multiplier (economics),Electronic engineering,CMOS,Multiplication,Integrated circuit | Journal |
Volume | Issue | ISSN |
14 | 2 | 0167-9260 |
Citations | PageRank | References |
2 | 1.11 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nick Kanopoulos | 1 | 34 | 12.44 |
| Joseph H. Carabetta | 2 | 2 | 1.11 |