| A Dual Rail Circuits Synthesis Environment For The Implementation Of Multiple Output Boolean Functions | 0 | 0.34 | 1998 |
| A Versatile Wireless System For Real-Time Telemetry Applications | 0 | 0.34 | 1996 |
| Tespad: A Testability Specifications Advisor For A Structured Test Methodology | 0 | 0.34 | 1996 |
| A New Efficient Dcvs Circuit Synthesis Technique Used For An Improved Implementation Of A Serial Parallel Multiplier | 0 | 0.34 | 1995 |
| Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction | 5 | 1.15 | 1995 |
| On the design of a high-performance, expandable, sorting engine | 0 | 0.34 | 1994 |
| Design and implementation of a high-performance, modular, sorting engine | 0 | 0.34 | 1994 |
| Multiple boundary scan-paths for minimizing circuit-board test-application time | 0 | 0.34 | 1994 |
| Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations | 1 | 0.39 | 1994 |
| Efficient board interconnect testing using the split boundary scan register | 0 | 0.34 | 1993 |
| A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port | 0 | 0.34 | 1992 |
| The split boundary scan register technique for testing board interconnects. | 2 | 0.40 | 1992 |
| A New Serial Parallel 2s Complement Multiplier For Vlsi Digital Signal-Processing | 7 | 0.82 | 1992 |
| Design And Implementation Of A Totally Self-Checking 16x16 Bit Array Multiplier | 2 | 1.11 | 1992 |
| On distributed fault simulation | 13 | 3.53 | 1990 |
| A bus-monitor unit for fault-tolerant system configurations | 0 | 0.34 | 1990 |
| Creating the IC palette [ASIC design]. | 1 | 0.41 | 1990 |
| A built-in test module for fault isolation | 2 | 0.43 | 1989 |
| Design of a bus-monitor for real-time applications | 1 | 0.48 | 1988 |
| Testing of Bit-Serial Signal Processors | 0 | 0.34 | 1983 |
