Name
Title | ||
|---|---|---|
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance |
Abstract | ||
|---|---|---|
A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the pro posed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conventional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabricated in 0.13 μm CMOS technology, the prototype digital CDR op erates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2 V supply. The pro posed clock-phase calibration is capable of correcting upto ±20% of input data duty-cycle error. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/JSSC.2011.2168872 | Solid-State Circuits, IEEE Journal of |
Keywords | Field | DocType |
CMOS integrated circuits,calibration,clock and data recovery circuits,frequency dividers,frequency locked loops,phase detectors,CMOS technology,bit rate 0.5 Gbit/s to 2.5 Gbit/s,clock-phase calibration,digital frequency-locked loop,digital half-rate clock and data recovery,frequency acquisition range,frequency detector,frequency dividers,half-rate bang-bang phase detector,input duty-cycle error tolerance,oscillator clock phases,power 6.1 mW,receiver timing margins,size 0.13 mum,sub-harmonic tone,voltage 1.2 V,Digital CDR,clock phase calibration,data duty cycle error,linear delay cell,optimal sampling,power spectral density of random NRZ data,reference-less frequency acquisition | Phase-locked loop,Half Rate,Data stream,Computer science,Duty cycle,Harmonic,Electronic engineering,Robustness (computer science),Voltage-controlled oscillator,Static timing analysis | Journal |
Volume | Issue | ISSN |
46 | 12 | 0018-9200 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajesh Inti | 1 | 118 | 13.20 |
| Wenjing Yin | 2 | 65 | 8.81 |
| Amr Elshazly | 3 | 242 | 28.08 |
| Naga Sasidhar | 4 | 28 | 4.29 |
| Pavan Kumar Hanumolu | 5 | 554 | 84.82 |