Name
Abstract | ||
|---|---|---|
In this paper, we present a new concept for modeling of interconnection networks in the field of massively parallel processor embedded architectures. The main focus of the paper is on two interconnection concepts, namely, interconnect-wrapper and DyRIBox definitions of reconfigurable interconnection networks. We compare both interconnection concepts against each other and formally prove their equality. Both concepts allow to model many different reconfigurable inter-processor networks efficiently. Furthermore, we point out how to define the interconnect using an architecture description language for massively parallel processor architectures called MAML. Finally, we demonstrate the pertinence of our approach by modeling and evaluation of different reconfigurable interconnect topologies. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1007/978-3-540-71270-1_20 | ARCS |
Keywords | Field | DocType |
dyribox definition,interconnection concept,different reconfigurable,parallel processor architecture,different reconfigurable inter-processor network,reconfigurable interconnection network,interconnection network,embedded architecture,parallel processor,architecture description language | Terminal and nonterminal symbols,Computer architecture,Processor array,Computer science,Massively parallel,Parallel computing,Network topology,Interconnection,Architecture description language | Conference |
Volume | ISSN | Citations |
4415 | 0302-9743 | 3 |
PageRank | References | Authors |
0.45 | 8 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexey Kupriyanov | 1 | 79 | 6.40 |
| Frank Hannig | 2 | 595 | 75.66 |
| Dmitrij Kissler | 3 | 78 | 7.30 |
| Jürgen Teich | 4 | 2886 | 273.54 |
| Julien Lallet | 5 | 10 | 1.39 |
| Olivier Sentieys | 6 | 597 | 73.35 |
| Sébastien Pillement | 7 | 100 | 17.33 |