Name
Abstract | ||
|---|---|---|
Embedded cores in a core-based system-on-chip (SOC) are not easily accessible via chip I/O pins. Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) have been proposed for the testing of embedded cores in a core-based SOC in a modular fashion. We show that such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the post-bond test time for 3D core-based SOCs under constraints on the number of TSVs, the TAM bitwidth, and thermal limits. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. It considers the Test Bus and TestRail architectures, and incorporates wire-length constraints in test-access optimization. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs. The test time dependence on various 3D parameters (e.g. 3D placement, the number of layers, thermal constraints, and the number of TSVs) is also studied. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1016/j.mejo.2010.06.015 | Microelectronics Journal |
Keywords | Field | DocType |
optimization technique,through silicon via,integer linear programming,core-based soc,test access mechanism,core-based system-on-chip,post-bond test time,randomized rounding,test wrapper,test time dependence,test time,three-dimensional integration,test-access mechanism optimization,soc test benchmarks,proposed optimization method,core-based socs,core-based three-dimensional socs,linear programming,system on chip,integrated circuits,lp relaxation,integer programming,system on a chip,testing,three dimensional,integrated circuit,optimization | Technology scaling,System on a chip,Computer science,Parallel computing,Real-time computing,Integer programming,Randomized rounding,Three-dimensional integrated circuit,Linear programming,Modular design,Integrated circuit,Embedded system | Journal |
Volume | Issue | ISSN |
41 | 10 | Microelectronics Journal |
Citations | PageRank | References |
24 | 1.85 | 39 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoxia Wu | 1 | 535 | 38.61 |
| Yibo Chen | 2 | 187 | 15.36 |
| K Chakrabarty | 3 | 8173 | 636.14 |
| Yuan Xie | 4 | 6430 | 407.00 |