Paper Info
Title
High-Level Synthesis System (HLDESA) for Processor Arrays
Abstract
In this paper, an approach to high-level synthesis of processor arrays is presented. In particular, we describe methods and tools of the system HLDESA for processor array design, which include resource constraints. Two major groups of resource constraints are considered: implementation constraints such as area and performance constraints to meet desired properties of the array as well as interface constraints such as communication constraints to ensure that the array can be embedded in a given environment. For integrating these two constraint types in the design process of processor arrays, several optimization problems are described, and the method of iterative co-partitioning is presented.
Year
DOI
Venue
2000
10.1109/PCEE.2000.873608
Trois-Rivieres, Que.
Keywords
Field
DocType
processor array design,high-level synthesis,implementation constraint,communication constraint,processor arrays,design process,interface constraint,resource constraint,processor array,high-level synthesis system,iterative co-partitioning,constraint type,design optimization,iterative methods,optimization,optimization problem,bandwidth,hardware,constraint optimization,high level synthesis,algorithm design and analysis,process design
Processor array,Computer science,Parallel computing,High-level synthesis,Engineering design process,Optimization problem,AS-Interface
Conference
ISBN
Citations 
PageRank 
0-7695-0759-X
2
0.39
References 
Authors
10
1
Name
Order
Citations
PageRank
Renate Merker115920.59