Name
Abstract | ||
|---|---|---|
The progress of design and fabrication technologies has led to an increase in small delay failures in systems-on-a-chip. To evaluate the delay testing quality accurately, the authors have already proposed a statistical approach that calculates actual sensitized path lengths that detect small delay defects in the transition delay test. However, the calculation requires a huge amount of CPU time. This paper presents a much more efficient method to calculate the sensitized longest path lengths and experimental results regarding CPU time and accuracy. Our experiments show that this calculation method has high speed and high accuracy. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TEST.2006.297622 | 2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2 |
Keywords | Field | DocType |
statistical analysis,system on chip,automatic test pattern generation,system on a chip,longest path | Delay calculation,Automatic test pattern generation,System on a chip,Computer science,CPU time,Real-time computing,Electronic engineering,Elmore delay,Longest path problem,Statistical analysis | Conference |
ISSN | Citations | PageRank |
1089-3539 | 4 | 0.45 |
References | Authors | |
16 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuji Hamada | 1 | 123 | 7.13 |
| Toshiyuki Maeda | 2 | 213 | 25.86 |
| Atsuo Takatori | 3 | 5 | 0.81 |
| Yasuyuki Noduyama | 4 | 4 | 0.45 |
| Yasuo Sato | 5 | 38 | 4.46 |