Name
Abstract | ||
|---|---|---|
Integrating large DRAM caches is a promising way to address the memory bandwidth wall issue in the many-core era. However, organizing and implementing a large DRAM cache imposes a trade-off between tag space overhead and memory bandwidth consumption. CHOP (Caching Hot Pages) addresses this trade-off through three filter-based DRAM-caching techniques. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/MM.2010.100 | international symposium on microarchitecture |
Keywords | Field | DocType |
cache storage,tag space overhead,tag space,cmp server,dram chips,cmp server platforms,memory hierarchy,memory bandwidth consumption,hardware,dram,memory bandwidth wall issue,filter-based dram-caching technique,hot pages,many-core era,emerging technologies,integrating dram caches,filter-based dram-caching techniques,chop,memory bandwidth,cache memories,filter cache,caching hot pages,large dram cache,memory management,resource management,radiation detector,radiation detectors,bandwidth,resource manager,cache memory,emerging technology | Dram,Resource management,Dram cache,Memory bandwidth,Memory hierarchy,Computer science,Parallel computing,Bandwidth (signal processing),Memory management,CAS latency | Journal |
Volume | Issue | ISSN |
31 | 1 | 0272-1732 |
Citations | PageRank | References |
23 | 0.86 | 8 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaowei Jiang | 1 | 43 | 2.25 |
| Niti Madan | 2 | 227 | 9.43 |
| Li Zhao | 3 | 604 | 34.84 |
| Mike Upton | 4 | 110 | 4.32 |
| Ravishankar K. Iyer | 5 | 1119 | 75.72 |
| Srihari Makineni | 6 | 600 | 37.89 |
| Don Newell | 7 | 512 | 32.67 |
| Yan Solihin | 8 | 2057 | 111.56 |
| Rajeev Balasubramonian | 9 | 2302 | 116.79 |