Name
Abstract | ||
|---|---|---|
This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - V-tn and therefore saves the active power in the half-selected columns (where V-tn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125 degrees C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the V-tn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-mu W/MHz writing energy and 72.8-mu W leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 mu W/MHz (12.9 pJ/access) at a supply voltage of 0.5 V and operating frequency of 6.25 MHz in a 50%-read/50%-write operation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transele.E95.C.572 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
SRAM, 8T, low energy, disturb, half select, write back | NMOS logic,Leakage (electronics),Process corners,CMOS,Static random-access memory,Electronic engineering,AC power,Transmission gate,Engineering,Threshold voltage | Journal |
Volume | Issue | ISSN |
E95C | 4 | 1745-1353 |
Citations | PageRank | References |
1 | 0.39 | 3 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shusuke Yoshimoto | 1 | 30 | 12.56 |
| Masaharu Terada | 2 | 8 | 2.25 |
| Shunsuke Okumura | 3 | 63 | 12.54 |
| Toshi-kazu Suzuki | 4 | 73 | 11.00 |
| Shinji Miyano | 5 | 85 | 12.63 |
| Hiroshi Kawaguchi | 6 | 395 | 91.51 |
| Masahiko Yoshimoto | 7 | 1 | 0.39 |