Name
Abstract | ||
|---|---|---|
The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We emulated many benchmark circuits on PBM128, and compared its memory size and computation time with the Intel's Core2Duo microprocessor. PBM128 requires approximately quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-00641-8_26 | ARC |
Keywords | Field | DocType |
sequential circuits,logic function,quaternary decision diagram,programmable interconnection,computation time,benchmark circuit,3-address quaternary branch instruction,program machine,core2duo microprocessor,parallel branching program machine,memory size,branching program,evaluation function,decision diagram | Sequential logic,Computer science,Program counter,Parallel computing,Microprocessor,Binary decision diagram,Real-time computing,Emulation,Interconnection,Electronic circuit,Computation | Conference |
Volume | ISSN | Citations |
5453 | 0302-9743 | 3 |
PageRank | References | Authors |
0.44 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroki Nakahara | 1 | 155 | 37.34 |
| Tsutomu Sasao | 2 | 1083 | 141.62 |
| Munehiro Matsuura | 3 | 189 | 24.44 |
| Yoshifumi Kawamura | 4 | 22 | 3.98 |