Paper Info
Title
A BIST TPG for Low Power Dissipation and High Fault Coverage
Abstract
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.
Year
DOI
Venue
2007
10.1109/TVLSI.2007.899234
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
lt-rtpg pattern,sequential circuits,switching activity reduction,proposed bist tpg,fault detection,integrated circuit testing,proposed bist,easy-to-detect fault,power dissipation,test pattern,low hardware overhead test,low power testing,circuit analysis computing,low power dissipation,random pattern testing,automatic test pattern generation,built-in self test,bist,fault diagnosis,high fault coverage,test sequences,benchmark circuit,vlsi,low hardware overhead test pattern generator,heat dissipation,3-weight wrbist,test sequence,built-in self-test (bist),cut,scan shift operations,iscas'89 benchmark circuits,power dissipation during test application,switching circuits,scan-based built-in self-test,lt-rtpg,fault coverage,heat dissipation during test application,circuit under test,large circuits,random sequences,3-weight weighed random bist,hardware,shift operator
Automatic test pattern generation,Sequential logic,Fault coverage,Circuit switching,Fault detection and isolation,Computer science,Real-time computing,Electronic engineering,Very-large-scale integration,Embedded system,Low-power electronics,Built-in self-test
Journal
Volume
Issue
ISSN
15
7
1063-8210
Citations 
PageRank 
References 
15
0.74
29
Authors
1
Name
Order
Citations
PageRank
Seongmoon Wang160548.50