Name
Abstract | ||
|---|---|---|
We propose an approach for locating logical faults in sequential circuits under the condition that all the internal nets are not observable. In this approach, candidates for the error sources are first deduced by an error propagation traceback starting from the failing primary outputs. Then, with the aid of probing, the possible error sources are found. Simulation results for ISCAS'89 benchmark circuits show that a reasonable diagnostic resolution can be achieved by our approach if more than 50% of the internal nets are observable. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/ATS.1997.643954 | Asian Test Symposium |
Keywords | Field | DocType |
possible error source,sequential circuit,benchmark circuit,error source,observable sequential circuit,simulation result,error propagation traceback,internal net,logical fault,reasonable diagnostic resolution,primary output,error propagation,computer science,sequential circuits,vlsi,error correction,probing | Propagation of uncertainty,Observable,Sequential logic,Computer science,Algorithm,Real-time computing,Electronic engineering,Electronic circuit | Conference |
ISBN | Citations | PageRank |
0-8186-8209-4 | 1 | 0.40 |
References | Authors | |
10 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Koji Yamazaki | 1 | 27 | 8.41 |
| Yamada, T. | 2 | 59 | 17.08 |