| Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture. | 0 | 0.34 | 2020 |
| Real-Time Image Processing Based On Service Function Chaining Using Cpu-Fpga Architecture | 0 | 0.34 | 2020 |
| Video Service Function Chaining with a Real-time Packet Reordering Circuit | 0 | 0.34 | 2018 |
| Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane | 0 | 0.34 | 2018 |
| A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model | 0 | 0.34 | 2017 |
| Accelerating SDN/NFV with Transparent Offloading Architecture. | 3 | 0.54 | 2014 |
| A Reliable Procedure In A New Power Management Technique For A 200-Gbps Packet Forwarding Lsi | 0 | 0.34 | 2013 |
| Diagnosing Resistive Open Faults Using Small Delay Fault Simulation | 1 | 0.37 | 2013 |
| Evaluation of transition untestable faults using a multi-cycle capture test generation method | 0 | 0.34 | 2010 |
| New Class of Tests for Open Faults with Considering Adjacent Lines | 2 | 0.38 | 2009 |
| Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC | 5 | 0.50 | 2009 |
| A Novel Approach for Improving the Quality of Open Fault Diagnosis | 5 | 0.49 | 2009 |
| Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information | 1 | 0.36 | 2008 |
| A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information | 0 | 0.34 | 2008 |
| Post-BIST Fault Diagnosis for Multiple Faults | 0 | 0.34 | 2008 |
| Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines | 5 | 0.49 | 2007 |
| Effective Post-BIST Fault Diagnosis for Multiple Faults | 1 | 0.39 | 2006 |
| Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset | 0 | 0.34 | 1999 |
| An approach to diagnose logical faults in partially observable sequential circuits | 1 | 0.40 | 1997 |
| A simple technique for locating gate-level faults in combinational circuits | 3 | 0.42 | 1995 |
| A Single Bridging Fault Location Technique for CMOS Combinational Circuits. | 0 | 0.34 | 1995 |
| A Single Bridging Fault Location Technique for CMOS Combinational Circuits. | 0 | 0.34 | 1995 |
