Name
Abstract | ||
|---|---|---|
We have implemented a novel bit-level matrix multiplier on a Xilinx FPGA chip where each processing element does a simple operation of adding three to six bits to generate one partial sum bit and one to two carryout bits. The speedup over word-level is possible because individual bits of a word do not have to be processed as a unit in a bit-level architecture. It is shown in a previous work that bit-level architectures for fixed point applications can be O(log p) times faster than the corresponding word-level architecture where p is the word length. In this paper we implemented the bit-level matrix multiplier on a Xilinx FPGA chip that is compared to a word-level matrix multiplier composed of highly optimized multiplier and adder macros available in the Xilinx Core generator library. The architecture presented in this paper is even faster than previous ones by breaking the critical path in the dependence graph into half. Our results show that speedup by a factor of 2 can be obtained in practice. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-44614-1_45 | FPL |
Keywords | Field | DocType |
fpga implementations,word-level matrix multiplier,bit-level architecture,bit-level matrix multiplier,corresponding word-level architecture,optimized multiplier,word-level matrix multipliers,xilinx fpga chip,previous work,log p,novel bit-level matrix multiplier,xilinx core generator library,critical path,fixed point,partial sums,chip | Adder,Computer science,Matrix (mathematics),Parallel computing,Field-programmable gate array,Multiplier (economics),Systems architecture,Critical path method,Matrix multiplication,Speedup | Conference |
ISBN | Citations | PageRank |
3-540-67899-9 | 2 | 0.44 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Radhika S. Grover | 1 | 9 | 2.33 |
| Weijia Shang | 2 | 347 | 36.80 |
| Qiang Li | 3 | 84 | 19.63 |