Name
Title | ||
|---|---|---|
Test Configuration Minimization for the Logic Cells of SRAM-Based FPGAs: A Case Study |
Abstract | ||
|---|---|---|
Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This paper presents a fast simulation-based method to compute an efficient seed (initial state) of a given primitive polynomial ... |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ETW.1999.804520 | ETW '99 Proceedings of the 1999 IEEE European Test Workshop |
Keywords | DocType | ISBN |
primitive polynomial,linear feedback shift registers,pseudo-random test pattern generator,efficient seed,logic cells,initial state,case study,bist scheme,test configuration minimization,fast simulation-based method,sram-based fpgas,field programmable gate arrays,computer aided software engineering,vlsi,fpga,minimization,test | Conference | 0-7695-0390-X |
Citations | PageRank | References |
5 | 0.52 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Renovell | 1 | 224 | 18.93 |
| J. M. Portal | 2 | 176 | 20.95 |
| J. Figueras | 3 | 227 | 19.91 |
| Y. Zorian | 4 | 499 | 47.97 |