Paper Info
Title
Energy efficient many-core processor for recognition and mining using spin-based memory
Abstract
Emerging workloads such as Recognition, Mining and Synthesis present great opportunities for many-core parallel computing, but also place significant demands on the memory system. Spin-based devices have shown great promise in enabling high-density, energy-efficient memory. In this paper, we present the design and evaluation of a many-core domain-specific processor for Recognition and Data Mining (RM) using spin-based memory. The RM processor has a two-level on-chip memory hierarchy consisting of a streaming access first-level memory and a random access second-level memory. Based on the memory access characteristics, we suggest the use of Domain Wall Memory (DWM) and Spin Transfer Torque Magnetic RAM (STT MRAM) to realize the first and second levels, respectively. We develop architectural models of DWM and STT MRAM, and use them to evaluate the proposed design and explore various architectural tradeoffs in the RM processor. We evaluate the proposed design by comparing it to a CMOS based design at the same 45nm technology node. For three representative RM algorithms (Support Vector Machines, k-means clustering, and GLVQ classification), the iso-area spin memory based design achieves an energy-delay product improvement of 1.5X -- 3X. Our results suggest that spin based memory technologies can enable significant improvements in energy efficiency and performance for highly parallel, data-intensive workloads.
Year
DOI
Venue
2011
10.1109/NANOARCH.2011.5941493
Nanoscale Architectures
Keywords
Field
DocType
memory system,memory technology,memory access characteristic,energy-efficient memory,access first-level memory,spin-based memory,iso-area spin memory,energy efficient many-core processor,rm processor,second-level memory,proposed design,domain wall,k means clustering,chip,semiconductor device modeling,data mining,dwm,random access,support vector machine,cmos integrated circuits,memory management,system on chip,parallel processing,parallel computer,energy conservation,energy efficient,stt mram,support vector machines
Interleaved memory,Semiconductor memory,Computer architecture,Extended memory,Uniform memory access,Computer science,Parallel computing,Memory management,Non-uniform memory access,Flat memory model,Memory architecture,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4577-0993-7
8
1.03
References 
Authors
10
5
Name
Order
Citations
PageRank
Rangharajan Venkatesan135019.87
Vinay K. Chippa245617.75
Charles Augustine3555.90
Kaushik Roy47093822.19
Anand Raghunathan55375415.27