Name
Title | ||
|---|---|---|
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs) |
Abstract | ||
|---|---|---|
Three-dimensional integrated circuits (3D ICs) have drawn groundswell of interest in both academia and industry in recent years. However, the power integrity of 3D ICs is threatened by the increased current density brought by vertical integration. To enhance reliability, the locations of power/ground through-silicon-vias (P/G TSVs), which are used to deliver power/ground signals to different layers, must be carefully placed to minimize IR-drop. However, the currents in 3D ICs are not deterministic and exhibit both spatial and temporal correlations. In view of this, we propose a correlation based heuristic algorithm for P/G TSV placement. Unlike most existing works, the proposed algorithm does not need iterations of full-grid simulations. Thus, it is especially attractive for large designs with millions of nodes. Experimental results on TSMC 90nm industrial designs indicate that the proposed method can achieve up to 70% reduction in IR-drop compared with the current industry practice, which uniformly distributes P/G TSVs. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISVLSI.2012.73 | ISVLSI |
Keywords | Field | DocType |
current industry practice,ground signal,full-grid simulations,power integrity,power-ground signals,reliable power delivery system design,three-dimensional integrated circuits,g tsv placement,tsmc industrial designs,heuristic algorithm,reliable power delivery,increased current density,temporal correlations,current density,ground through-silicon-vias,correlation,proposed algorithm,integrated circuit design,system design,size 90 nm,g tsvs,3d ic,vertical integration,p-g tsv,spatial correlation,ir-drop,ir drop,power-ground through-silicon-vias,through-silicon-via,through silicon via | Power network design,Heuristic (computer science),Power integrity,Electronic engineering,Through-silicon via,Integrated circuit design,Three-dimensional integrated circuit,Vertical integration,Engineering,Integrated circuit | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-4673-2234-8 | 1 |
PageRank | References | Authors |
0.35 | 9 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pei-Wen Luo | 1 | 74 | 8.22 |
| Tao Wang | 2 | 1 | 0.35 |
| Chin-Long Wey | 3 | 316 | 56.51 |
| Liang-Chia Cheng | 4 | 37 | 6.46 |
| Bih-Lan Sheu | 5 | 8 | 1.04 |
| Yiyu Shi | 6 | 553 | 83.22 |